The present invention relates generally to semiconductor devices and photomasks and more particularly to semiconductor device fabrication using a photomask designed using modeling and empirical testing.
The manufacture of semiconductor devices is heavily dependent on the accurate replication of computer-aided-design (CAD) generated patterns onto the surface of a device substrate. The replication process is typically performed using optical lithography followed by a variety of subtractive (e.g., etch) and additive (e.g., deposition) processes. Optical lithography patterning involves the illumination of a metallic coated quartz plate known as a photomask which contains a magnified image of the computer generated pattern. This illuminated image is reduced in size and patterned into a photosensitive film on the substrate.
As a result of the interference and processing effects which occur during pattern transfer, images formed on the substrate deviate from their ideal dimensions and shape as represented by the computer images. These deviations depend on the characteristics of the patterns as well as on a variety of process conditions. Because these deviations can significantly effect the performance of the semiconductor device, many approaches have been pursued which focus on CAD compensation schemes which ensure a resultant ideal image.
One such compensation scheme utilizes the selective biasing of mask patterns to compensate for the pattern distortions occurring during wafer processing. The term Optical Proximity Correction (OPC) is commonly used to describe this process of selective mask biasing, even though the trend exists to include pattern distortions unrelated to the optical image transfer. The idea of biasing patterns to compensate for image transfer infidelities has been commonly applied to E-beam lithography to counteract the effects of back scattered electrons, both in the writing of photo masks and in direct wafer writing operations.
Another known compensation technique is to add assist features, otherwise known as scattering bars or intensity leveling bars, to the photomask. Assist features are sub-lithographic features placed adjacent to a feature that is to be printed. Since these additional features are sub-lithographic, they will not be transferred to the resist during printing. They will, however, aid in sharpening the image that is printed.
In one aspect, the present invention is intended to correct the proximity effects that can cause severe pattern fidelity distortion on a wafer patterned by a lithographic process. This distortion is generally caused by aerial image effects as well as other contributors such as resist and etch. The total deviation from nominal created by these effects can create errors as great as 100 nm or more. Optical proximity correction (OPC), usually implemented as an automatic full-chip software solution, can be used to correct for the effects by modifying the mask pattern accordingly.
State of the art OPC solutions are making attempts to describe the overall process variation as accurately as possible and turn this error model into some correction model to be applied xe2x80x9cin totalxe2x80x9d during automatic OPC to adjust the mask accordingly. Errors remaining from this kind of approach are easily in the range of tens of nanometers. These remaining errors are typically caused by the many error-adding steps included in the CD data collection and analysis process and in the limitations of building exact error and correction models as well as the generally high critical dimension errors that must be corrected for.
In one aspect, the present invention proposes a method that can be used for performing OPC, such that the deviations from design are first corrected with a xe2x80x9cwell knownxe2x80x9d model, typically a pure aerial image model, and then the residual error is corrected for by an empirical model obtained from a test mask that has gone through the same xe2x80x9cwell knownxe2x80x9d first correction as the design.
Accordingly, the preferred embodiment of the invention provides a method for correcting a given design from proximity effects. The method uses multiple correction passes such that known, typically major, effects are corrected in a first pass (or first passes) and the remaining errors are corrected in a second (or subsequent) pass hence minimizing the overall remaining error of the correction to a minimum.
As an example, an initial design may include a set of ideal patterns, e.g., patterns used to evaluate the process. These patterns would be modified (corrected) using a known model such as an aerial image model to adjust for patterning inaccuracy. A test mask would then be fabricated and a test structure or structures formed using the test mask. The patterns formed on the surface of the test chip would then be measured and compared with the ideal patterns. Based on this comparison, a remaining error model describing the remaining differences between the dimensions of the printed test patterns and the ideal patterns is generated. The already modified (corrected) set of ideal patterns can now be corrected even further in a second pass using the xe2x80x9cremaining error modelxe2x80x9d as process description and the modified (corrected) set of ideal patterns as input.
A photomask could then be generated as by first applying the aerial image based OPC followed by correcting using the xe2x80x9cremaining error modelxe2x80x9d. Such a photomask can be a memory chip, processor or any other logic device that is then transferred to the surface of the wafers with high accuracy, meaning minimizing the differences between the dimensions of the ideal patterns (e.g., circuit designer""s intent) and the printed pattern.